During development of hardware chips for system servers, like System z® servers of the applicant, International Business Machines Corporation, of Armonk, N.Y., USA, each chip is simulated and verified in different environments before it is physically manufactured. The simulation or test environments differ in the level of detail, the scope e.g. multi chip versus single chip models, and the ecosystem where the simulation is executed. To initialize a system server, a complex sequence for each of its chips is needed. As the simulation or test environments are very different, the languages to formulate initialization sequences are also very different. Therefore the initialization sequences are manually rewritten during the transition from one environment to the next. This process is error prone.
During system hardware bring up different simulation models are used on different levels and environments to verify chip initialization sequences. When changing the simulation model it needs to be guaranteed that the initialization sequences do not inadvertently change also. This is currently not possible in an automated fashion.
In U.S. Pat. No. 6,285,914 B1, a chip verification method by comparing internal state traces of chips having various functions is disclosed. The disclosed chip verification method is capable of reducing the overall chip designing and verifying time and attaining a more exact verification. The disclosed chip verification method in a chip design stage includes a first step of executing an application program for each of a target system having a target chip and a system having a function verification chip model of a design stage, using a virtual system modeled by a hardware description language, a second step of storing an internal state of the target chip on a command-by-command basis during execution of the application program and generating a trace file, a third step of comparing the internal state of the target chip stored at the trace file and an internal state of the function verification chip model on a command-by-command basis; and a fourth step of continuing execution of the program if the respective internal states are the same from the above comparison result, and if different, outputting the internal state and ending execution. However the disclosed chip verification method is not capable to show the functional equivalence of a system with multiple chips.